Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. Extreme ultraviolet (EUV) lithography based patterning is being considered as a serious candidate for the sub-10 nm nodes. One challenge of EUV technology is that EUV resists tend to have a lower etch selectivity and worse line edge roughness (LER) and line width roughness (LWR) than traditional 193 nm resists. Consequently, the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.
Sub 30 nm node semiconductor manufacturing has imposed many challenges on the physical limits of traditional lithography techniques. There is a demand for alternative patterning strategies which involve augmentation of 193i lithography with LELE (Litho-Etch-Litho-Etch), SADP (Self Aligned Double Patterning) and SAQP (Self Aligned Quadruple Patterning). However, multiple patterning schemes bring additional challenges in the form of edge placement error, higher costs due to a larger number of passes through lithography and other processing steps, and the introduction of pitch walking at several processing steps.